Performance Engineer, Hardware - Palo Alto, CA
$200,000 - $420,000 USD yearly
Originally posted 15 May 2026 by the employer.
About the role
This role architects, models, and correlates high-performance custom silicon, developing simulators to evaluate how AI accelerator architectures and SoC systems execute real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators while collaborating across compiler, software, and RTL teams.
What you'll do
- Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC. - Conduct micro-architectural exploration and "what-if" studies to evaluate architectural changes—including cache sizes, branch predictors, pipeline depths, scatter/gather, and matmul shaping—and measure impact on IPC, MFU, TTFT, and total execution time. - Analyze and profile AI kernels and software stacks to generate representative traces that stress-test hardware models. - Collaborate with compiler and kernel teams on HW/SW co-design to optimize software mapping to hardware. - Validate and correlate performance models against RTL and pre-silicon emulators within strict tolerance levels. - Identify and quantify system-level bottlenecks ranging from instruction-level parallelism (ILP) limits to bandwidth throttling and utilization.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, and 5+ years of practical industry experience working with advanced process nodes (7nm or below). - Expert proficiency in C/C++ or event-driven simulation environments like SystemC. - Hands-on experience with compiler transformations (LLVM/GCC/XLA) and execution of high-performance kernels (CUDA/Triton) interacting with the underlying ISA. - Expert knowledge in Computer Architecture of at least one architecture style, including SoCs, CPUs, GPUs, or AI accelerators. - Experience profiling hardware with performance counters, hardware profilers, and trace analysis tools to dissect application behavior.
Nice to have
- Hands-on experience in pre-silicon RTL/emulator and/or post-silicon performance validation. - Knowledge or experience of QEMU models for pre-silicon software development. - Proficiency in scripting for data post-processing, visualization of simulation results, and automation of massive regression suites.
Skills: performance engineers, AI accelerator, hardware models, Micro-architectural Exploration, HW/SW Co-Design
This role has been open 130 days — well above the 85-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
509
|
Median days open
85 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | River | All employers we track in this specialty (509 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 509 |
| Open roles in the wider Software, Firmware & Systems family | 7 | 6298 · 144 employers |
| Median days open | 130 d | 85 d (+45 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: performance engineers, AI accelerator, hardware models, Micro-architectural Exploration, HW/SW Co-Design
Who's hiring in this category
- Qualcomm · 104 open roles · median 114 d
- NVIDIA · 89 open roles · median 56 d
- AMD · 38 open roles · median 96 d
- Micron Technology · 27 open roles · median 58 d
- Mobileye · 20 open roles · median 83 d
- Analog Devices · 18 open roles · median 41 d
How we counted: 509 open AI/ML Hardware Engineering (AI ML Hardware) roles from 75 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.