Pe Logic Design - United States
$127,400 - $236,600 USD yearly
About the role
This role involves micro-architecture and design of memory controllers for data centers and AI applications.
What you'll do
- Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
- Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data.
- Collaborate closely with verification team to shape test plans and improve verification coverage.
- Work with physical design team to understand and resolve timing, power, and congestion challenges.
- Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary.
- Provide technical support to FAE team on pre-sales customer engagements.
What you'll need
- Strong System Verilog/Verilog RTL design expertise.
- Questa/Incisive/VCS simulator experience.
- Python/Perl/TCL scripting experience.
- 10+ years of logic design experience (ASIC/FPGA) with BSEE, or 8+ years of logic design experience (ASIC/FPGA) with MSEE.
Nice to have
- ASIC synthesis, timing constraint, CDC/RDC experience.
- UVM Verification experience.
- Memory (HBM, LPDDR) expertise.
- AMBA AXI or CHI design experience.
Skills: RTL design, System Verilog, micro-architecture, PPA, timing constraint
This role has been open 38 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
964
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Rambus | All employers we track in this specialty (964 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 964 |
| Open roles in the wider Digital Design & Verification family | 23 | 3050 · 114 employers |
| Median days open | 123 d | 62 d (+61 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, System Verilog, micro-architecture, PPA, timing constraint
Who's hiring in this category
- Qualcomm · 139 open roles · median 60 d
- AMD · 67 open roles · median 62 d
- Synopsys · 63 open roles · median 22 d
- NXP Semiconductors · 54 open roles · median 70 d
- Analog Devices · 46 open roles · median 35 d
- NVIDIA · 46 open roles · median 51 d
How we counted: 964 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 27 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.