PDK Enablement Engineer - Folsom, CA, United States
$190,000 USD yearly
Originally posted 7 October 2026 by the employer.
Collaborate on PDK compatibility for FinFET and gate-all-around (GAA) nodes.
About the role
This role involves ensuring PDK compatibility and performance, developing documentation, and troubleshooting PDK-related issues. You will be working with external foundry’s FinFET and gate-all-around (GAA) nodes.
What you'll do
- Collaborate with CAD teams, tool vendors, and foundries to ensure PDK compatibility and performance. - Develop and maintain documentation for PDK usage and best practices. - Troubleshoot and resolve PDK-related problems. - Conduct training sessions for design teams on PDK usage and updates. - Participate in std cell characterization activities digital flow evaluation post design environment set up. - Drive continuous improvement initiatives to enhance PDK features and usability.
What you'll need
- Master’s degree in Electrical Engineering, Computer Engineering or related field and 2 years of experience. - Experience working with EDA tools and flows. - Proficiency in scripting languages including Python/Perl/Shell. - Experience with parasitic extraction, physical verification, circuit simulation, and reliability verification. - Experience working on external foundry’s FinFET and gate-all-around (GAA) nodes. - Experience in PDK development. - Understanding of semiconductor manufacturing processes and design rules.
This role has been open 2 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 704 |
| Open roles in the wider Physical Implementation family | 72 | 1488 · 107 employers |
| Median days open | 101 d | 79 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Who's hiring in this category
- Cadence Design Systems · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology (this employer) · 44 open roles · median 107 d
- Qualcomm · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.