PD Timing lead - Bangalore-Technostar B3, India
Originally posted 29 September 2026 by the employer.
About the role
This role is responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. The engineer will own SDC methodology and timing signoff quality.
What you'll do
- Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC).
- Perform comprehensive timing analysis and closure for full-chip and partition-level designs.
- Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.
- Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.
- Own timing signoff readiness and ensure timing quality across all project deliverables.
- Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field.
- 7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design.
- Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV.
- Hands-on experience developing and validating SDC constraints.
- Proficiency with Synopsys PrimeTime and timing signoff methodologies.
- Proficiency in Tcl, Python, Perl, or Shell scripting.
Nice to have
- Experience driving full-chip timing closure for large CPU, GPU, AI/ML, networking, or datacenter SoCs.
- Expertise in constraint quality checks, timing signoff reviews, and correlation methodologies.
- Knowledge of clock-domain crossings, asynchronous interfaces, and timing exception verification.
- Experience with PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, or equivalent EDA tools.
- Familiarity with low-power timing methodologies, UPF flows, and advanced-node signoff requirements.
- Experience supporting tapeouts at 5nm, 4nm, 3nm, or newer process technologies.
- Experience developing automation, AI-assisted timing analysis flows, and productivity-enhancing methodologies.
Skills: timing constraints, timing analysis, PrimeTime, SDC, timing signoff
This role has been open 28 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 63 | 682 |
| Open roles in the wider Physical Implementation family | 91 | 1507 · 111 employers |
| Median days open | 31 d | 66 d (−35 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: timing constraints, timing analysis, PrimeTime, SDC, timing signoff
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD (this employer) · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.