PCB Layout Engineer - AI Compute Hardware - Mountain View (HQ) or Remote
$160,000 - $275,000 USD yearly
Originally posted 28 August 2026 by the employer.
About the role
MatX is looking for a PCB Layout Engineer to design and deliver high-speed, high-power, high-density printed circuit boards for its AI chip, compute tray, and rack-scale platform. In this hands-on role, layout execution directly impacts signal integrity, power integrity, and system performance across large-scale LLM training and inference infrastructure.
What you'll do
- Own PCB layout from floorplanning through final Gerber release for complex, high-layer-count boards including AI accelerator boards, compute trays, and backplanes. - Design high-speed differential pair and controlled impedance routing for PCIe Gen5/6, CXL, and Ethernet 112G/224G interfaces, applying length matching and timing constraints per SI/PI guidelines. - Plan stack-ups (layer assignment, impedance control, via structure, and laminate selection) and route complex BGA packages, including AI ASICs. - Design power delivery networks (PDN) covering VRM placement, decoupling capacitors, and power planes, collaborating with SI/PI engineers on pre- and post-layout simulations. - Ensure DFM/DFT/DFA compliance (test points, via-in-pad, back-drill, and assembly constraints) while coordinating with mechanical engineers on board outline and chassis limits. - Lead design, layout, and DFM reviews with JDM/ODM partners and manage fabrication release packages (Gerbers, drill files, stackup specifications, and footprint libraries). - Support bring-up, lab debug, and signal probing to resolve board layout issues.
What you'll need
- 7+ years of PCB layout experience, including complex multi-layer boards (20+ layers) for server, AI compute, networking, or high-performance hardware. - Strong proficiency in Cadence Allegro (or equivalent EDA tool), with expertise in differential pair routing, impedance control, length matching, reference planes, and via optimization. - Hands-on experience with fine-pitch BGA placement and routing for AI ASICs, GPUs, or high-density packages, alongside high-speed interfaces including PCIe Gen5/6, CXL, DDR5, and 112G/224G SerDes. - Thorough understanding of PDN design (VRM placement, decoupling strategy, power planes, and return paths) and stack-up engineering (Megtron 6/8/9, TU-953Q). - Direct experience with back-drilling, via-in-pad, DFM/DFT requirements (copper balance, test point coverage, solder mask), and interpreting SI/PI simulation results. - Proven track record generating and releasing fabrication packages directly to PCB fabricators and JDM/ODM partners.
Nice to have
- Experience with 5nm or 3nm and below AI ASIC board layout, ultra-fine pitch BGA, and high-density routing. - Experience with 224G PAM4 high-speed interface routing and material selection. - Knowledge of fiber weave effect mitigation, including routing at 45° and spread glass laminates. - Familiarity with OCP Open Rack board form factors and mechanical constraints. - Experience with power integrity simulation tools such as Ansys SIwave or Cadence Sigrity. - Background in EMI/EMC design, stitching vias, ground guard traces, and shielding techniques.
This role has been open 54 days — slightly above the 51-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
1003
|
Median days open
51 d
|
Median salary
$155k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | MatX | All employers we track in this specialty (1003 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 1003 |
| Open roles in the wider Software, Firmware & Systems family | 35 | 6291 · 145 employers |
| Median days open | 58 d | 51 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $155k |
Who's hiring in this category
- Intel Corporation · 72 open roles · median 34 d
- KLA Corporation · 63 open roles · median 48 d
- Teradyne · 61 open roles · median 34 d
- NVIDIA · 53 open roles · median 72 d
- Applied Materials · 51 open roles · median 70 d
- AMD · 46 open roles · median 52 d
How we counted: 1003 open Hardware Systems Engineering (AI ML Hardware) roles from 104 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.