Package Layout Engineer - Mountain View, CA, United States
$165,000 - $225,000 USD yearly
Originally posted 6 August 2026 by the employer — open 45 days.
Work on the physical layout of AI accelerator silicon packages.
About the role
This role involves owning the physical layout of advanced packages for AI accelerator silicon, taking multi-die 2.5D and 3D packages from bump map through tapeout release. You will define substrate and interposer stackups, plan bump and ball maps, route high-density escape and HBM-class channels, and build the power delivery for accelerators.
What you'll do
- Own package substrate and interposer layout end to end, including stackup definition, bump and ball map planning, RDL and escape routing, and design release to substrate suppliers and OSATs.
- Own die-to-package-to-board co-design, partnering with physical design on bump placement and floorplan and with PCB layout on the package-board interface.
- Close package DRC/LVS and netlist verification against OSAT and substrate vendor design rules, and drive rule negotiation where the design requires it.
What you'll need
- Exceptional abilities in advanced package physical layout: multi-die substrate and interposer routing, high-density escape, power and ground plane design for high-current accelerator rails, and stackup and via structure definition.
- 8+ years of package layout experience on high-performance designs, including 2.5D / 3D and multi-die packages (CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies).
- Hands-on with industry-standard package layout tools (Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer, or equivalent) and package DRC/LVS flows.
- Demonstrated ability to work closely with architecture, physical design, SI/PI, thermo-mechanical, and OSAT partners to converge and sign off complex package designs.
Skills: package substrate layout, interposer layout, multi-die 2.5D and 3D packages, RDL and escape routing, Cadence Allegro Package Designer
This role has been open 9 days — well below the 37-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
67
|
Median days open
37 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (67 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 67 |
| Median days open | 9 d | 37 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: package substrate layout, interposer layout, multi-die 2.5D and 3D packages, RDL and escape routing, Cadence Allegro Package Designer
Who's hiring in this category
- Micron Technology · 13 open roles · median 142 d
- AMD · 6 open roles · median 26 d
- Marvell Technology · 6 open roles · median 12 d
- Broadcom · 5 open roles · median 162 d
- NVIDIA · 5 open roles · median 37 d
- Amazon · 4 open roles · median 25 d
How we counted: 67 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.