Package Design Engineer - Staff
$154,000 - $252,800 USD yearly
Originally posted 15 July 2026 by the employer.
About the role
The Package Design Engineer leads advanced package selection, package/SiP physical design and layout, optimization, design verification, and tape out. The position supports data center applications as part of the Qualcomm Data Center team.
What you'll do
- Own and drive advanced package selection, package structure, and configuration optimization for server solutions. - Execute Package/SIP physical design, layout, optimization, design verification (DV), and tape out. - Implement the physical design of packages and modules for SoC architectures while optimizing mechanical, electrical, and thermal performance. - Interface with cross-functional groups on new product package/SiP feasibility analysis, pin out optimization, and SI/PI requirements. - Define and develop design verification and automation strategies to strengthen package design and release flows. - Partner with the BU PD team to optimize chip floorplan, bump placement, and package size.
What you'll need
- Proficiency in Cadence APD & SiP tools. - Fundamental knowledge of high-speed IO interfaces and electromagnetic field concepts. - Understanding of IC packaging structures, chip-package, and package-board interactions. - Fundamental knowledge of electronic packaging processes and failure modes.
Nice to have
- Master's degree in Electrical Engineering, Mechanical Engineering, Material Science, or a related field with 5 years of experience. - Experience with package configurations and assembly/substrate technology including Flip chip BGA and 2.5D/3D Interposer. - Familiarity with SI/PI tools such as XtractIM, PowerSI, HFSS, or Q3D, including package model extraction, S-parameters, and RLGC models. - Understanding of high-speed interfaces such as DDR, PCIe, and UCIE. - Experience using the Calibre tool, conducting package design reviews, and applying high-speed layout constraints such as crosstalk mitigation and differential pairs. - Solid understanding of substrate manufacturing processes, Design Rules Check (DRC), and Design for Manufacturing (DFM).
Skills: advanced package selection, Package/SIP physical design, 2.5D/3D Interposer, Cadence APD & SiP, high-speed IO interfaces
This role has been open 96 days — well below the 119-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
40
|
Median days open
119 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (40 roles · 19 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 40 |
| Median days open | 113 d | 119 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: advanced package selection, Package/SIP physical design, 2.5D/3D Interposer, Cadence APD & SiP, high-speed IO interfaces
Who's hiring in this category
- Qualcomm (this employer) · 5 open roles · median 112 d
- Intel Corporation · 4 open roles · median 36 d
- Marvell Technology · 4 open roles · median 103 d
- Micron Technology · 4 open roles · median 159 d
- NVIDIA · 4 open roles · median 71 d
- GlobalFoundries · 3 open roles · median 39 d
How we counted: 40 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 19 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.