Package Design Engineer - Signal and Power Integrity (TERADYNE, North Reading, MA)
$111,300 - $178,200 USD yearly
Originally posted 5 October 2026 by the employer.
About the role
This role involves package design and signal and power integrity development for advanced measurement ASIC products within the Semiconductor Test Division.
What you'll do
- Support ASIC package signal and power integrity development, including package stackup evaluation and return-path control.
- Develop and review package and PCB layout constraints for high-speed serial links, clocks, and power rails.
- Apply electromagnetic and transmission-line principles to evaluate interconnects in time and frequency domains.
- Build, review, and document simulation models for insertion loss, return loss, crosstalk, and power-distribution performance.
- Support package-level power-distribution-network analysis, including target impedance, decoupling strategy, and current density.
- Collaborate with ASIC design, PCB design, thermal, mechanical, test, and manufacturing teams.
What you'll need
- Bachelor of Science in Electrical Engineering (BSEE) or a closely related electrical engineering discipline.
- Two or more years of relevant engineering experience in semiconductor packaging, high-speed digital or mixed-signal hardware, signal integrity, power integrity, PCB design, package design, modeling, or validation.
- Working knowledge of electromagnetic field and transmission-line fundamentals, impedance control, reflections, crosstalk, high-speed signaling, and power-distribution concepts.
- Experience or coursework using time-domain and frequency-domain analysis methods, S-parameters, circuit simulation, or electromagnetic field solvers.
- Familiarity with package and PCB design concepts, fabrication, assembly, and design-for-manufacture considerations.
Nice to have
- Experience with Cadence tools; experience with Ansys, HyperLynx, ADS, HFSS, SPICE, or comparable tools.
- Familiarity with IBIS, IBIS-AMI, or SPICE-class models.
- Experience using laboratory equipment such as a VNA, TDR/TDT, or high-speed oscilloscope.
- Programming or automation experience with Python, Tcl, MATLAB, Perl, C/C++, C#, Visual Basic, or similar tools.
Skills: Package Design, Signal Integrity, Power Integrity, ASIC products, high-speed serial links
This role has been open 0 days — well below the 61-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
196
|
Median days open
61 d
|
Median salary
$161k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (196 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 196 |
| Open roles in the wider Process, Fab & Equipment family | 98 | 9631 · 109 employers |
| Median days open | 9 d | 61 d (−52 d vs this employer) |
| Median salary (USD postings) | — | $161k |
Skills observed across this category: Package Design, Signal Integrity, Power Integrity, ASIC products, high-speed serial links
Who's hiring in this category
- Infineon Technologies · 25 open roles · median 47 d
- Renesas Electronics · 22 open roles · median 37 d
- Micron Technology · 20 open roles · median 143 d
- onsemi · 13 open roles · median 20 d
- Monolithic Power Systems · 11 open roles · median 200 d
- Intel Corporation · 9 open roles · median 161 d
How we counted: 196 open Packaging Engineering (Packaging) roles from 44 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.