Optical Network Engineer - Mountain View, CA, United States
$120,000 - $250,000 USD yearly
Originally posted 15 July 2026 by the employer.
About the role
This senior engineering role focuses on the design, qualification, and productization of optical interconnect technologies for AI scale-up and scale-out networks across pluggables, NPO, and CPO. You will own the full lifecycle from component characterization and link budget analysis to system-level bring-up and data center deployment.
What you'll do
- Validate and productize high-speed copper and optical connectivity solutions for AI accelerator systems, leading vendor due diligence and onboarding for 1.6T products including AEC and pluggable optical transceivers. - Characterize and qualify optical modules across DSP Optics, LRO, LPO, NPO, and CPO architectures for 800G and 1.6T deployments in scale-up AI fabrics. - Perform link budget analysis and evaluate performance metrics including TDECQ, OMA, and stressed receiver sensitivity. - Evaluate transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, VCSEL-based MMF links, and EML-based SMF solutions. - Define optical interconnect strategies and model end-to-end link budgets for 1.6T (200G/lane PAM4) across SMF, MMF, and MCF fiber types in AI cluster topologies. - Manage technical vendor engagements with optical module and silicon photonics suppliers while driving NPI qualification plans, yield improvement, and reliability testing.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Optical Engineering, Physics, or Photonics. - 7–12+ years of experience in optical interconnect engineering, including at least 3 years focused on data center or AI fabric applications. - Hands-on experience qualifying 400G, 800G, or 1.6T optical modules in production environments. - Knowledge of PAM4 signal theory, SerDes architecture, and optical link physics at 200G per lane. - Proficiency with optical test equipment, including BERT, OTDR, optical spectrum analyzers, sampling oscilloscopes, optical power meters, and TDECQ testers. - Experience with OIF-CEI and IEEE 802.3dj electrical and optical compliance specifications. - Experience with link budget modeling tools such as MATLAB, Python-based photonic simulation, or GNPY.
Nice to have
- Background in AI accelerator or GPU system validation. - Familiarity with JEDEC or PCIe compliance testing methodologies. - Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization.
This role has been open 97 days — well above the 52-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
973
|
Median days open
52 d
|
Median salary
$155k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | MatX | All employers we track in this specialty (973 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 973 |
| Open roles in the wider Software, Firmware & Systems family | 35 | 6222 · 145 employers |
| Median days open | 56 d | 52 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $155k |
Who's hiring in this category
- Intel Corporation · 76 open roles · median 36 d
- KLA Corporation · 65 open roles · median 46 d
- Teradyne · 56 open roles · median 32 d
- NVIDIA · 52 open roles · median 67 d
- Applied Materials · 50 open roles · median 68 d
- AMD · 46 open roles · median 50 d
How we counted: 973 open Hardware Systems Engineering (AI ML Hardware) roles from 101 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.