OPC Technology Transfer Engineer (R&D) - Dallas, TX, United States
Originally posted 22 October 2026 by the employer.
About the role
As an OPC Technology Transfer Engineer within the Advanced Technology Development (ATD) organization, you will bridge the gap between initial R&D development and High-Volume Manufacturing (HVM) by owning the full lifecycle of transferring developed OPC technologies to production Fabs. You will analyze process, equipment, layout, and tool disparities across Photolithography and Etching to predict, mitigate, and resolve transfer risks prior to recipe release.
What you'll do
- Analyze process, equipment, layout, and tool disparities between R&D and HVM environments to resolve transfer risks before recipe release. - Align transferred OPC solutions with production-line physics and hardware characteristics across Photolithography and Etching processes. - Partner with manufacturing operators, shift technicians, and Fab staff to coordinate test wafer execution and maintain technical alignment. - Collect, analyze, and interpret large-scale wafer measurement datasets to evaluate OPC recipe performance for manufacturing sign-off. - Compile and analyze high-volume SEM images and Critical Dimension (CD) data to verify R&D software model behavior against physical production silicon. - Analyze automated OPC verification results to identify lithographic critical care-abouts and select metrology targets for systematic layout review and CD-SEM measurement tracking.
What you'll need
- Masters in Electrical Engineering, Physics, Computer Science, Chemistry, or a related degree. - 5+ years of experience in semiconductor photolithography and/or OPC development. - Lithography & RET expertise for 45nm, 28nm, 22nm, or 20nm processing nodes. - Hands-on experience handling high-volume SEM measurement data and image inspections. - Strong layout review skills using OPC verification tools to determine and isolate critical metrology targets. - Understanding of OPC development flows, process window optimization, and design rule constraints.
Nice to have
- Knowledge of advanced lithography processes, lithography simulation techniques, mask making, and RET techniques used in semiconductor manufacturing and process development. - Familiarity with physical layout (gds/oas), litho/OPC test pattern design, test pattern generators, and layout software such as Virtuoso and KLayout. - Programming experience in a Unix environment. - Understanding of OPC pattern validation methodologies and process window assessment techniques such as KLA’s Photolithography Wafer Qualification (PWQ).
Skills: OPC, Photolithography, CD-SEM, RET, Technology Transfer