On/Off-Chip SI/PI Engineer - San Jose, CA, United States
$150,000 - $320,000 USD yearly
Originally posted 28 July 2026 by the employer — open 44 days.
This role focuses on SI/PI analysis for HBM and DRAM products.
About the role
This role provides hands-on SI/PI analysis to resolve immediate HBM challenges and contributes to the development of advanced architectures for future HBM and DRAM products.
What you'll do
- Drive system-level co-optimization beyond standalone DRAM design.
- Verify system-level SI/PI robustness through integrated modeling and 3D electromagnetic analysis.
- Analyze root causes of SI/PI issues and establish improvement plans.
- Participate in technical engagements with key customers.
What you'll need
- BS in Electrical Engineering or a related field with 3+ years of relevant experience in SI/PI engineering, or MS/Ph.D with a focus on signal/power integrity, high-speed signaling, electromagnetics, or RF/microwave engineering.
- Understanding of 2.5D/3D IC architectures, modeling and operations.
- Hands-on experience in SI/PI analysis, including on-chip PDN, off-chip PDN, and high-speed channel analysis.
- Proficiency with SI/PI simulation and analysis tools (HFSS, SIwave, Sigrity, ADS, HSPICE).
Nice to have
- Experience with package/PCB layout review tools (Allegro Design/APD).
- AI-assisted analysis and automation skills.
Skills: SI/PI analysis, HBM, DRAM, high-speed channel analysis, 3D electromagnetic analysis, on-chip PDN, off-chip PDN, HFSS
This role has been open 43 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 43 d | 91 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI analysis, HBM, DRAM, high-speed channel analysis, 3D electromagnetic analysis, on-chip PDN
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.