NVIDIA 2027 Internships: Hardware Verification - CA, Santa Clara, United States
$20 - $71 USD yearly
Originally posted 19 August 2026 by the employer.
About the role
This internship involves hardware verification within NVIDIA's teams, focusing on projects with measurable business impact.
What you'll do
- Debug using tools like Verdi, DVE, and Questa
- Work with simulation and formal verification tools such as JasperGold or Cadence Jasper
- Conduct random functional testing and write test plans
- Develop directed and random diagnostics
- Verify GPU or processor architectures
What you'll need
- Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
- Course or internship experience with SystemVerilog and UVM (Universal Verification Methodology)
- Experience with VLSI Design or Digital Design
- Knowledge of Functional Coverage or Assertion-Based Verification (ABV)
- Prior experience with Verilog, VHDL, Perl, TCL, C, C++, or Python
- Familiarity with Linux environments
Skills: SystemVerilog, UVM, Functional Coverage, Assertion-Based Verification, Formal Verification
This role has been open 58 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 86 | 1195 |
| Open roles in the wider Digital Design & Verification family | 235 | 3198 · 115 employers |
| Median days open | 58 d | 64 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, Functional Coverage, Assertion-Based Verification, Formal Verification
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA (this employer) · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.