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NVIDIA 2027 Internships: Hardware Design for Test (DFT) - CA, Santa Clara, United States

NVIDIA US, CA, Santa Clara, United States Internship 2 months ago
Verification, Validation & Test

Originally posted 19 August 2026 by the employer.

About the role

This internship focuses on Hardware Design for Test (DFT) for current and future products. Interns will work on projects with measurable business impact.

What you'll do

  • Process Hardware Design for Test (DFT) internship applications.
  • Work on projects related to DFT.

What you'll need

  • Actively enrolled in a university pursuing an M.S. or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
  • Anticipated graduation date (month and year) clearly indicated on resume or CV.
  • Course or internship experience related to Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug.
  • Scan Chain Design and ATPG, Boundary Scan and JTA, Memory BIST (Built-In Self-Test), Logic BIST and Compression (EDT, Streaming Scan Network), At-Speed and Delay Testing.
  • Prior experience or knowledge of Perl, TCL, C, C++, Python, Synopsys, TetraMAX, Cadence Modus, Linux.
Market context

This role has been open 58 days — slightly above the 57-day median for DFT Engineering roles.

DFT Engineering · DFT Test

Open roles in category
243
Median days open
57 d
Median salary
$203k
See the full market breakdown ▾Category comparison, and who else is hiring
How NVIDIA compares in DFT Engineering hiring
Metric NVIDIA All employers we track in this specialty (243 roles · 53 employers)
Open roles in this specialty 23 243
Open roles in the wider Digital Design & Verification family 235 3198 · 115 employers
Median days open 34 d 57 d (−23 d vs this employer)
Median salary (USD postings) — $203k

Who's hiring in this category

  • AMD · 39 open roles · median 42 d
  • NVIDIA (this employer) · 24 open roles · median 38 d
  • Qualcomm · 24 open roles · median 102 d
  • NXP Semiconductors · 18 open roles · median 64 d
  • Synopsys · 13 open roles · median 24 d
  • Micron Technology · 10 open roles · median 63 d

How we counted: 243 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
US, CA, Santa Clara, United States
On-site
Internship
2 months ago

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