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Teradyne

NPI Manufacturing Engineer (MEMORY TEST DIVISION, San Jose, CA)

Teradyne San Jose, CA, United States Contract 2 months ago
Verification, Validation & Test

$108,200 - $173,200 USD yearly

Originally posted 10 August 2026 by the employer.

About the role

This role involves joining the New Product Introduction (NPI) team within the Nextest Division, focusing on bringing new products to market.

What you'll do

  • Collaborate on product build processes with design engineering
  • Develop and implement new assembly instruction procedures
  • Develop Manufacturing Process Strategy for outsourced products
  • Drive Design for Manufacturability (DFM) reviews through the New Product Introduction process
  • Design manufacturing fixtures, including validation, build, documentation, and handoff to high volume production
  • Create and implement Engineering Change Notices to update BOMs and drawings
  • Monitor and drive quality standards at suppliers and internally
  • Develop and provide training to assembly personnel and contract manufacturers

What you'll need

  • BS Degree in Mechanical Engineering, Industrial Technology, or related field
  • 5+ years of experience with electro-mechanical assemblies
  • Experience in SolidWorks and CAD applications
  • Ability to perform structured problem solving
  • Flexible to work with global suppliers across multiple time zones
  • Ability to travel ~10%

Nice to have

  • Hands on assembly experience is preferred
Market context

This role has been open 68 days — well above the 29-day median for Silicon Test Engineering roles.

Silicon Test Engineering · DFT Test

Open roles in category
553
Median days open
29 d
Median salary
$173k
See the full market breakdown ▾Category comparison, and who else is hiring
How Teradyne compares in Silicon Test Engineering hiring
Metric Teradyne All employers we track in this specialty (553 roles · 78 employers)
Open roles in this specialty 75 553
Open roles in the wider Silicon Validation & Test family 92 2218 · 113 employers
Median days open 24 d 29 d (−5 d vs this employer)
Median salary (USD postings) — $173k

Who's hiring in this category

  • Teradyne (this employer) · 76 open roles · median 23 d
  • Renesas Electronics · 43 open roles · median 23 d
  • Infineon Technologies · 41 open roles · median 39 d
  • Micron Technology · 29 open roles · median 33 d
  • Qualcomm · 28 open roles · median 29 d
  • Texas Instruments · 23 open roles · median 24 d

How we counted: 553 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

Apply now
San Jose, CA, United States
On-site
Contract
$108,200 - $173,200 USD yearly
2 months ago

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