Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Originally posted 3 June 2026 by the employer.

Focuses on C and SystemC performance modeling for HBM-based memory subsystems and advanced packaging.

About the role

This role leads HBM performance modeling, analysis, and optimization of high-bandwidth memory subsystems for SoCs. The work spans architecture exploration from early concept through post-silicon correlation.

What you'll do

- Develop and maintain C / SystemC performance models for HBM-based memory subsystems. - Define and execute experiments to evaluate HBM architecture features, memory controller behavior, and system-level trade-offs. - Identify performance bottlenecks across HBM, interconnect, caches, and compute, and propose architecture improvements. - Collaborate with cross-functional teams including SoC, NoC, memory controller, power, and software to influence design decisions. - Research and track industry trends and developments in HBM, 3D-stacked memory, and advanced packaging. - Support post-silicon performance characterization, correlation, and model refinement.

What you'll need

- Bachelor's degree in Science, Engineering, or a related field with 4+ years of relevant experience, or a Master's degree with 3+ years, or a PhD with 2+ years of ASIC design, verification, validation, integration, or related experience. - 3+ years of experience in performance modeling, memory architecture, or system architecture. - Strong C proficiency and experience with SystemC/TLM modeling. - Solid understanding of memory hierarchies and DRAM systems.

Nice to have

- Hands-on experience with HBM2/HBM2E/HBM3 architectures. - Experience with AI/ML, GPU, or HPC-class SoCs. - Familiarity with post-silicon performance analysis and silicon correlation.

Skills: HBM, performance modeling, SystemC, memory architecture, SoC architecture