Next Gen, High-Speed, Memory and Cache Controller Design Engineer
$101,400 - $152,200 USD yearly
Originally posted 7 October 2026 by the employer.
About the role
The team focuses on enabling high-speed (1Ghz) designs and interfacing with CPUs, GPUs, DSPs, and multimedia processors.
What you'll do
- Develop or contribute to architectural and design specifications.
- Drive the micro-architecture of portions of the logic design.
- Implement and deliver RTL and collaborate with verification engineers for high-quality designs.
- Debug designs and provide debug support for chip integration.
- Perform Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, and Power Analysis.
What you'll need
- Bachelor's or Master's degree in Science, Engineering, or a related field.
- Experience with LPDDR memory and cache controller.
- Experience with NoC based architectures, especially front-end interfacing to CPU, DSP, and multimedia processors.
- Exposure to HBM memory type designs.
- Experience with on-chip tightly coupled SRAM & L3 cache controller architecture/design.
- Experience with x86 or ARM CPU/bus architectures.
- Experience with ordering of memory transactions and methods to enforce proper ordering to conform to ISA architecture specification.
Nice to have
- 3 years of experience (for early-career professionals).
Skills: HBM/LPDDR/DDR memory controller, memory systems, RTL coding, cache controller, memory transactions
This role has been open 1 day — well below the 65-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
303
|
Median days open
65 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (303 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 303 |
| Median days open | 93 d | 65 d (+28 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM/LPDDR/DDR memory controller, memory systems, RTL coding, cache controller, memory transactions
Who's hiring in this category
- Micron Technology · 153 open roles · median 86 d
- Synopsys · 33 open roles · median 49 d
- Qualcomm (this employer) · 18 open roles · median 92 d
- Broadcom · 17 open roles · median 50 d
- SanDisk · 17 open roles · median 36 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 303 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.