Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Digital Design & SoC Architecture
Originally posted 22 July 2026 by the employer.
About the role
What you'll do
- Develop or contribute to architecture and design specifications.
- Drive the micro-architecture of portions of the logic design.
- Implement and deliver RTL for high-speed memory subsystems.
- Work with verification engineers to ensure high quality designs.
- Debug designs and provide debug support when integrated into the chip.
- Make regular contributions to design methodology improvements.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or a related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- 5 years ASIC design, RTL coding, front-end digital design experience.
- 3 years Hardware Architecture experience.
- Experience with LPDDR memory and cache controller, NoC based architectures interfacing to CPU, DSP, and multimedia processors.
- Experience with on-chip tightly coupled SRAM & L3 cache controller architecture/design.
- Experience with x86 or ARM CPU/bus architectures, including ordering of memory transactions and methods to enforce proper ordering.
Nice to have
- Exposure to RTL Design Verification flows.
- Exposure to HBM memory type designs.
Market context
This role has been open 74 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 139 | 968 |
| Open roles in the wider Digital Design & Verification family | 374 | 3109 · 114 employers |
| Median days open | 59 d | 62 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm (this employer) · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.