Next Gen CPU Power Management RTL Design Engineer - CA, Santa Clara, United States
Originally posted 18 September 2026 by the employer — open 0 days.
Design core clocking, reset, and power management IP for Ryzen, Threadripper, or Epyc CPUs.
About the role
The work directly impacts AMD’s Ryzen, Threadripper, or Epyc CPU product lines.
What you'll do
- Design and develop microarchitecture for core clocking, reset, and power management IP. - Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP. - Define specifications and documentation for IP microarchitecture and interfaces. - Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance. - Develop C/C++ firmware for IP initialization, configuration, and control. - Perform RTL linting, clock domain crossing (CDC) analysis, and related checks for design correctness.
What you'll need
- MS in EE, ECE, Computer Engineering, or Computer Science. - 5+ years of experience in RTL design and microarchitecture for processors or complex IP. - Proficiency in Verilog/SystemVerilog for RTL design and verification. - Strong C/C++ development experience, including embedded firmware for power management. - Solid understanding of digital design fundamentals: synchronous/asynchronous design, CDC, multi-voltage, and power-aware design. - Knowledge of low-power methodologies (clock gating, power gating, DVFS).
Nice to have
- Experience with processor power management architectures (DVFS, P-state/C-state control, power-performance optimization). - Expertise in hardware/firmware interactions for power control, sequencing, and system-level flows. - Familiarity with clock distribution, clock gating, CDC methodologies, and reset design in complex SoCs. - Experience with power gating, retention, isolation, and multi-voltage domain design on advanced nodes. - Understanding of thermal management, power budgeting, throttling, and reliability considerations. - Background in design-for-debug and design-for-test (scan, ATPG, MBIST, silicon observability). - Validation experience across simulation, emulation, and silicon bring-up.
This role has been open 0 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
941
|
Median days open
60 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (941 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 941 |
| Open roles in the wider Digital Design & Verification family | 249 | 3012 · 114 employers |
| Median days open | 60 d | 60 d (same as this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 52 d
- AMD (this employer) · 63 open roles · median 60 d
- Synopsys · 58 open roles · median 29 d
- NXP Semiconductors · 53 open roles · median 66 d
- NVIDIA · 47 open roles · median 43 d
- Analog Devices · 39 open roles · median 72 d
How we counted: 941 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.