New College Grad - Mixed Signal Design Engineer, HBM - Richardson, TX, United States
Originally posted 1 September 2026 by the employer.
This role focuses on the digital and mixed-signal foundation for High Bandwidth Memory (HBM) products.
About the role
This role is for a New College Grad Mixed Signal Design Engineer focusing on the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products.
What you'll do
- Define and implement digital micro-architecture for HBM base-die subsystems.
- Develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures.
- Develop, integrate, and debug synthesizable SystemVerilog RTL, including multi-channel logic, interrupt handling, register maps, scan infrastructure, and design-for-test interfaces.
- Work with design verification teams to build verification strategies, reach coverage goals, and perform CDC/RDC analysis.
- Support silicon bring-up and post-silicon validation through debug enablement, root-cause analysis, and partnership with DFT and test engineering teams.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with digital design, SoC integration, or semiconductor development through academic projects, internships, research, or industry experience.
- Solid understanding of SystemVerilog RTL development, clock and reset architectures, CDC/RDC methodologies, and low-power design concepts.
- Understanding of design-for-debug and design-for-test principles.
- Ability to collaborate effectively within multi-functional engineering teams.
- Experience working in AI-Assisted or AI-Enabled environments, or demonstrated willingness to apply AI tools to support engineering workflows, debug activities, and technical analysis.
Nice to have
- Exposure to post-silicon validation, silicon bring-up, or structured hardware debug methodologies.
- Familiarity with scan, MBIST, LBIST, or related test and debug architectures.
- Experience contributing to verification planning and partnering with design verification teams to achieve functional and and code coverage objectives.
- Knowledge of micro-architecture optimization, timing closure concepts, and design tradeoffs related to constraints and path intent.
- Experience Applying AI, Employing AI, or Using AI for data analysis, debug automation, productivity enhancement, or performance optimization within semiconductor design environments.
Skills: HBM base-die, digital micro-architecture, SystemVerilog RTL, clock and reset architectures, design-for-test
This role has been open 33 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM base-die, digital micro-architecture, SystemVerilog RTL, clock and reset architectures, design-for-test
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.