New College Grad - HBM Layout Engineer - Jalisco, Mexico
Originally posted 5 June 2026 by the employer.
About the role
This role involves designing layouts for leaf cells, standard cells, or sub-blocks, applying a systematic approach to IC layout design.
What you'll do
- Design layout for leaf cells, standard cells, or sub-blocks
- Apply a systematic, meticulous, and methodical approach to IC layout design
- Interpret DRC/LVS and other physical verification checks to ensure design accuracy
- Proactively plan work to meet project timelines
- Collaborate effectively with internal teams for layout project execution
What you'll need
- Bachelor’s, Master’s, or PhD in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related fields
- Graduation within the last 2 years (Bachelor’s, Master’s, or PhD)
- Strong knowledge of electronic circuit concepts
- Experience using circuit simulation and design tools
- English communication skills (conversational level required)
Nice to have
- Internship or academic project experience in pre-silicon circuit design
- Understanding of pre-silicon development areas such as analog circuits and physical design
- Basic knowledge of MOS concepts, semiconductor fabrication, and analog layout fundamentals
- Experience with programming or scripting languages (C++, Python)
- Familiarity with tools such as Cadence VLE/VXL and Mentor Graphics Calibre (DRC/LVS) or similar
- Understanding of layout trade-offs including speed, capacitance, power, and area
- Interest in developing problem-solving skills in physical verification and custom layout
Skills: HBM Layout, leaf cells, standard cells, IC layout design, DRC/LVS, Cadence VLE/VXL
This role has been open 121 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM Layout, leaf cells, standard cells, IC layout design, DRC/LVS, Cadence VLE/VXL
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.