Network Systems Architect - Sunnyvale, CA, United States
Originally posted 18 September 2026 by the employer.
About the role
This role defines the scale out and scale-up network architecture for current and future Cerebras platforms, including proprietary accelerator interconnects, protocols, and switching.
What you'll do
- Set the multi-generation architecture and roadmap for Cerebras scale-up networks and their interfaces to scale-out and customer-facing networks.
- Understand mapping and communication choices from application, compiler, runtime, and communication-library teams, then derive required bandwidth, latency, ordering, availability, and serviceability.
- Define fabric topology, protocols, and switch behavior, including routing, buffering, flow control, reliability, and fault containment.
- Decide when to use standards-based technology or merchant silicon and when a custom protocol, switch, link, or offload is justified.
- Use performance models, traffic simulation, prototypes, and lab data to test architecture choices and set acceptance criteria.
- Write architecture and interface specifications, lead design reviews, and drive cross-layer decisions through implementation, bring-up, and qualification.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 12 or more years of relevant industry experience, including principal-level technical ownership of a major networking, switching, accelerator, or HPC system from architecture into implementation or deployment.
- Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture, with data-plane depth to reason about switch pipelines, buffering, routing, flow or congestion control, and reliability.
- Experience deriving network requirements from incomplete workload and system information, with the range to make decisions across software, accelerator I/O, topology, and physical constraints.
- Working knowledge of Ethernet, IP, and RDMA, plus conceptual familiarity with BGP and EVPN and the tradeoffs between routed networks and simpler low-latency scale-up designs.
- Architectural judgment grounded in prior implementation, modeling, silicon, lab, bring-up, or debugging work.
Nice to have
- Proprietary accelerator interconnects or scale-up technologies such as NVLink, xGMI, TPU ICI, Xe Link, or UALink-class systems.
- Switch ASIC, NIC or DPU, accelerator I/O, transport offload, collective acceleration, coherent memory, or custom-fabric work.
- FPGA architecture or mapping experience, or work with other placement-sensitive systems where topology materially affects communication.
- AI or HPC communication stacks such as NCCL, RCCL, MPI, SHMEM, or proprietary collective libraries.
- RoCE, InfiniBand, PCIe, CXL, or other relevant scale-out and I/O technologies.
- Workload-driven modeling, traffic simulation, emulation, or pre-silicon and post-silicon correlation.
- Working awareness of SerDes, packaging, retimers, cabling, optics, and reach constraints.
Skills: network architecture, accelerator interconnects, low-latency scale-up, fabric topology, performance models, AI platform
This role has been open 25 days — well below the 80-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
453
|
Median days open
80 d
|
Median salary
$234k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cerebras | All employers we track in this specialty (453 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 453 |
| Open roles in the wider Digital Design & Verification family | 6 | 3166 · 114 employers |
| Median days open | 25 d | 80 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $234k |
Skills observed across this category: network architecture, accelerator interconnects, low-latency scale-up, fabric topology, performance models, AI platform
Who's hiring in this category
- Qualcomm · 72 open roles · median 84 d
- NVIDIA · 59 open roles · median 67 d
- AMD · 35 open roles · median 63 d
- Apple · 34 open roles · median 7 d
- Arm Holdings · 27 open roles · median 110 d
- NXP Semiconductors · 21 open roles · median 112 d
How we counted: 453 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.