MTS, Physical Design (AI2532) - Bengaluru, India
Originally posted 17 August 2026 by the employer — open 33 days.
About the role
This role involves full-chip floorplanning, integration, and Place and Route (P&R) for complex SoCs, along with P&R flow development.
What you'll do
- Perform hands-on Testchip/SoC/Full-chip floorplanning, integration, and P&R, including P&R flow development.
- Establish integration plans for dies with optimization for package and board constraints.
- Execute bump planning, die file generation, and close the loop with the package team on signal and power bump placement restrictions.
- Derive specifications and collaterals for IP blocks to execute floorplan and automatic place and route (APR) at subsequent hierarchies.
- Perform integration of all dies in a package and complete relevant checks before tape-out.
What you'll need
- BE/BTech with at least 10+ years of experience on high complexity SoC designs.
- Successfully completed at least one SoC in 7nm or lower process technology.
- Knowledge and implementation strategies to create an IO ring in accordance with design specifications.
- Knowledge of ESD, latch-up, foundry requirements, and placement strategies.
- Experience with PG creation and push-down methodologies.
- Understanding of Analog components and their placement requirements.
- Knowledge of RDL and experience working with packaging for SoC floorplan design.
Nice to have
- In-depth knowledge of Physical Verification tools like Synopsys ICV & Calibre Physical Verification Tools.
- Knowledge of Package PV checks, IO/Bump PV cleanup, PV rules viz. Antenna, Density, DFM, DFY, DPT at lower technology nodes 7nm or less.
Skills: floorplanning, P&R, SoC integration, 7nm, IO ring
This role has been open 2 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
603
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiMa.ai | All employers we track in this specialty (603 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 603 |
| Open roles in the wider Physical Implementation family | 2 | 1371 · 106 employers |
| Median days open | 41 d | 58 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: floorplanning, P&R, SoC integration, 7nm, IO ring
Who's hiring in this category
- Qualcomm · 108 open roles · median 41 d
- Broadcom · 38 open roles · median 68 d
- NVIDIA · 38 open roles · median 49 d
- AMD · 35 open roles · median 38 d
- Synopsys · 27 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 45 d
How we counted: 603 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.