MTS - HIG HBM - ARCHITECTURE - Richardson, TX, United States
Originally posted 18 September 2026 by the employer.
About the role
This role involves building and owning the end-to-end design quality system for High Bandwidth Memory (HBM) products.
What you'll do
- Architect high-speed IO for HBM products.
- Define and standardize the IO design quality process from architecture to silicon.
- Correlate silicon measurements and simulation performance for circuit level design analysis.
- Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure design quality.
What you'll need
- Prior industrial experience in high-speed clocking design at 32Gbps+ speed.
- IO circuit design background with familiarity of both analog and digital design and simulation experience.
- Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits.
- Familiarity with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI.
- MS or PhD in EE with 10+ years of relevant Engineering or Design Engineering experience on high-speed IO, PLL, Tx, Rx, Equalization, clock tree.
Nice to have
- Prior circuit debug experience through Product Engineering or equivalent.
- Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D).
Skills: high-speed IO design, HBM products, 32Gbps+ clocking design, circuit verification, advanced packaging
This role has been open 25 days — well below the 80-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
80 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (244 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 48 | 1414 · 105 employers |
| Median days open | 73 d | 80 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed IO design, HBM products, 32Gbps+ clocking design, circuit verification, advanced packaging
Who's hiring in this category
- AMD · 31 open roles · median 40 d
- Synopsys · 31 open roles · median 28 d
- Cadence Design Systems · 19 open roles · median 186 d
- Qualcomm · 19 open roles · median 60 d
- Micron Technology (this employer) · 13 open roles · median 73 d
- Apple · 12 open roles · median 14 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.