MTS - ESD Design Engineer - Bengaluru, India
Originally posted 9 April 2026 by the employer — open 154 days.
This role focuses on ESD architecture and protection strategy for high-speed I/O portfolios, including HBM, DDR, and LPDDR PHY I/Os.
About the role
This role involves defining and owning ESD architecture and protection strategy for high-speed I/O portfolios and leading ESD–I/O co‑design trade‑off decisions. The role focuses on delivering production silicon meeting aggressive ESD and performance targets for sophisticated, high‑volume products.
What you'll do
- Define and own ESD architecture and protection strategy for high-speed I/O portfolios, including HBM, DDR, LPDDR PHY I/Os, PCIe, USB, Ethernet, and MIPI.
- Lead ESD–I/O co‑design trade‑off decisions, balancing aggressive ESD targets with ultra‑low capacitance and leakage requirements.
- Perform and guide ESD circuit design and analysis at block and full‑chip level, establishing simulation methodologies for transient ESD stress.
- Own ESD modeling correlation by working with device/modeling teams on compact models and driving correlation between SPICE simulations, TLP/VF‑TLP, and silicon results.
- Lead silicon-level ESD failure analysis across products and generations, driving root cause analysis for HBM/CDM failures, leakage, performance degradation, latch‑up, and substrate‑coupling issues.
- Define company-wide layout guidelines for ESD devices, including current uniformity, ballasting, guard rings, substrate/well engineering, and power clamp placement.
What you'll need
- B.Tech / M.Tech / PhD in Electrical / Electronic Engineering or related team.
- 15+ years of hands‑on experience in ESD circuit design and protection architecture.
- 15+ years of hands‑on experience in high-speed I/O or mixed-signal chip environments.
- Deep expertise in HBM, CDM, MM, latch‑up mechanisms.
- Deep expertise in high-speed signal integrity fundamentals and constraints.
- Strong command of SPICE-based simulators (Spectre, HSPICE) and physical layout review and ESD signoff flows.
Skills: ESD architecture, high-speed I/O, HBM, DDR, LPDDR PHY, PCIe, USB, Ethernet, MIPI
This role has been open 139 days — well above the 66-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
259
|
Median days open
66 d
|
Median salary
$156k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (259 roles · 46 employers) |
|---|---|---|
| Open roles in category | 33 | 259 |
| Median days open | 45 d | 66 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $156k |
Skills observed across this category: ESD architecture, high-speed I/O, HBM, DDR, LPDDR PHY, PCIe
Who's hiring in this category
- Micron Technology (this employer) · 33 open roles · median 45 d
- Texas Instruments · 30 open roles · median 111 d
- NXP Semiconductors · 15 open roles · median 65 d
- Renesas Electronics · 14 open roles · median 53 d
- onsemi · 13 open roles · median 111 d
- Semtech · 11 open roles · median 83 d
How we counted: 259 open Analog IC Design (Analog Design) roles from 46 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.