MTS, AI Optimized Memory Digital Design Engineer
Originally posted 4 August 2026 by the employer.
About the role
This role involves translating architectural vision into efficient, silicon-proven hardware implementations for tightly coupled, high-performance memory architectures for AI. It focuses on balancing performance, power, area, and reliability while influencing critical design decisions.
What you'll do
- Translate architecture requirements into scalable microarchitectures and drive implementation through silicon.
- Design, implement, and review SystemVerilog RTL for advanced memory system architectures.
- Perform synthesis and early PPA analysis to optimize area, power, and timing.
- Develop and maintain microarchitecture documentation that aligns design intent across teams.
- Evaluate architectural and implementation tradeoffs to support technical decision-making.
What you'll need
- Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
- Strong experience in digital design and microarchitecture development with ownership of hardware blocks from specification through implementation.
- Solid understanding of computer architecture and memory systems, including SoC-level behaviors and tradeoffs.
- Experience with synthesis flows and early PPA estimation and optimization.
- Proficiency in SystemVerilog and at least one programming language such as C, C++, or Python.
Nice to have
- Master’s or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
- 5+ years of industry experience delivering silicon-proven memory systems or SoC hardware designs on modern process nodes.
- Familiarity with memory interfaces, reliability features, and media management concepts.
- Experience influencing architecture features with a strong understanding of RTL implementation cost and feasibility.
- Experience working with Agentic AI tools to assist with design and verification.
This role has been open 61 days — below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 968 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 61 d | 62 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.