Modeling Architect - Austin, Texas, United States
Originally posted 4 September 2026 by the employer — open 17 days.
This role focuses on the T100 optical inference accelerator.
About the role
This role involves hands-on architecture modeling of the T100 optical inference accelerator with hardware/software co-design.
What you'll do
- Bring up inference workloads including dense and Mixture of Experts (MoE) transformers, hybrid/SSM models, and quantization.
- Bind Hugging Face and PyTorch workloads to the programming model and run them on the functional model.
- Co-design tiling, scheduling, the instruction set architecture (ISA), the SRAM and High Bandwidth Memory (HBM) hierarchy, and multi-chip mapping.
- Build in one or more layers of the modeling stack: roofline and limiter studies; Python energy and latency models; C++ functional models; cycle-approximate performance and power models; and RTL simulation with Verilator and SystemVerilog.
- Own the tests, configs, and plots behind a result.
- Share results with architects, compiler, runtime, and RTL teams, and incorporate their feedback into the model stack.
What you'll need
- 3+ years of experience in hardware modeling, performance simulation, or computer architecture.
- Proficiency in Python or modern C++ (C++17 or later).
- Working knowledge of computer architecture and microarchitecture, including pipelines, caches, memory hierarchies, and instruction set architecture (ISA).
- Ability to turn an LLM, GEMM, or accelerator paper into a workload config using Hugging Face or PyTorch.
- Strong debugging skills and documentation habits.
Nice to have
- MS or PhD in Computer Engineering, Electrical Engineering, or Computer Science.
- Experience with roofline analysis, limiter analysis, GPU benchmarking, or model correlation.
- Event-driven, cycle-approximate, or cycle-accurate simulation with SystemC, gem5, or SST.
- SystemVerilog, Verilog, Verilator, or RTL co-simulation.
- Memory and interconnect experience with HBM, DRAM, cache, SRAM, network-on-chip (NoC), AXI, or DMA.
- Familiarity with CUDA, GPU programming, or PyTorch internals.
Skills: optical inference accelerator, hardware/software co-design, architecture performance models, functional models, RTL simulation
This role has been open 17 days — well below the 67-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
516
|
Median days open
67 d
|
Median salary
$232k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (516 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 516 |
| Open roles in the wider Software, Firmware & Systems family | 10 | 5829 · 143 employers |
| Median days open | 17 d | 67 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $232k |
Skills observed across this category: optical inference accelerator, hardware/software co-design, architecture performance models, functional models, RTL simulation
Who's hiring in this category
- Qualcomm · 106 open roles · median 99 d
- NVIDIA · 85 open roles · median 67 d
- AMD · 43 open roles · median 62 d
- Micron Technology · 32 open roles · median 39 d
- Mobileye · 25 open roles · median 53 d
- Analog Devices · 14 open roles · median 24 d
How we counted: 516 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.