MLA Design Verification Engineer I, Annapurna Labs - Cupertino, California, United States
Originally posted 15 October 2026 by the employer.
About the role
As an MLA Design Verification Engineer I, you will be responsible for the design and optimization of hardware in data centers, including technologies such as AWS Inferentia.
What you'll do
- Verify and validate hardware and software solutions achieve desired functionality.
- Develop multi-faceted verification and validation plans.
- Execute multi-faceted verification and validation plans.
- Measure team progress towards customer metrics.
What you'll need
- Experience in verifying and validating hardware and software solutions.
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1195 |
| Open roles in the wider Digital Design & Verification family | 26 | 3198 · 115 employers |
| Median days open | 27 d | 64 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.