MLA Design Verification Engineer I, Annapurna Labs - Austin, Texas, United States
Originally posted 1 July 2026 by the employer. Relisted by the employer on 15 September 2026.
Work on AWS Inferentia machine learning acceleration hardware at Annapurna Labs.
About the role
As a member of the Cloud-Scale Machine Learning Acceleration team at Annapurna Labs, you will be responsible for the design and optimization of hardware in Amazon Web Services (AWS) data centers. This includes working on technologies such as AWS Inferentia for machine learning inference and FPGA acceleration.
What you'll do
- Verify and validate hardware and software solutions to achieve their desired functionality. - Develop and execute multi-faceted verification and validation plans. - Measure and track progress toward customer metrics. - Contribute to the hardware and software co-design of machine learning acceleration systems.
What you'll need
- Experience or academic background in design verification and hardware validation. - Knowledge of hardware and software co-design principles for machine learning or FPGA acceleration. - Ability to develop and execute multi-faceted verification plans.
Skills: verification, validation plans, Inferentia, hardware solutions
This role has been open 112 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1220 |
| Open roles in the wider Digital Design & Verification family | 21 | 3283 · 116 employers |
| Median days open | 25 d | 64 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: verification, validation plans, Inferentia, hardware solutions
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.