MLA Design Verification Engineer, Annapurna Labs - Austin, Texas, United States
Originally posted 29 September 2026 by the employer.
Verify hardware and software solutions for Trainium and Inferentia silicon.
About the role
This role involves verifying and validating hardware and software solutions for cloud server platforms, ensuring desired functionality.
What you'll do
- Verify and validate hardware solutions.
- Verify and validate software solutions.
- Develop multi-faceted verification plans.
- Execute multi-faceted verification plans.
- Measure team progress towards customer metrics.
Skills: hardware verification, software validation, ML Accelerator, Trainium, Inferentia
This role has been open 9 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1189
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1189 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 1189 |
| Open roles in the wider Digital Design & Verification family | 25 | 3183 · 114 employers |
| Median days open | 40 d | 64 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: hardware verification, software validation, ML Accelerator, Trainium, Inferentia
Who's hiring in this category
- Qualcomm · 106 open roles · median 43 d
- AMD · 103 open roles · median 50 d
- NVIDIA · 74 open roles · median 64 d
- Synopsys · 61 open roles · median 26 d
- SiFive · 54 open roles · median 67 d
- Cadence Design Systems · 51 open roles · median 109 d
How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.