ML/AI Timing and Power Flow Engineer - San Jose, California, United States

Originally posted 9 October 2026 by the employer.

About the role

This role involves developing and optimizing ML/AI Timing and Power Flows for ASIC/FPGA implementation flows.

What you'll do

• Develop, enhance, and maintain timing and power flows across the physical design and signoff lifecycle.
• Own and drive STA flows, including timing setup, analysis, and timing collateral generation.
• Design and implement power-aware flows, including UPF integration, power intent validation, and comprehensive power/timing reporting.
• Lead standard-cell and macro library generation and characterization flows, including timing, power, noise, and constraint characterization.
• Build and maintain scalable, automated flow infrastructure using coding and software engineering practices.

What you'll need

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of relevant industry experience in ASIC or FPGA timing/power/library flow development.
• 6+ years of experience in timing and power flow development and methodology.
• 6+ years of experience with industry-standard STA, power analysis, and library characterization tools.
• 6+ years of experience with coding practices (Tcl, Python, Perl, or similar), focused on clean, reusable, and maintainable flow infrastructure.
• 6+ years of experience with deep understanding of timing concepts, STA methodologies, timing constraints, and timing collateral generation.
• 6+ years of experience in power analysis, optimization techniques, and comprehensive power reporting methodologies.
• 6+ years of hands-on experience with library generation and characterization, including timing, power, and noise model development and validation.
• 6+ years of experience working with UPF, including multi-power-domain designs and power intent modeling.
• 6+ years of experience in timing collateral generation, library integration into STA/power flows, and complex flow automation coding.
• Demonstrated ML/AI enthusiasm, with interest or experience in applying data-driven techniques to flow automation, debug, QoR prediction, or trend analysis.

Nice to have

• 5+ years of experience supporting advanced-node, large-scale, complex SoC designs.
• 3+ years of experience working with ML/AI frameworks, data analytics platforms, or statistical methods applied to EDA, timing/power analysis, or library characterization flows.
• 5+ years of experience performing deep data analysis and translating quantitative insights into measurable flow, timing, power, or library methodology improvements.
• 5+ years of demonstrated experience independently driving methodology enhancements end-to-end, from problem definition through deployment and production adoption.
• 5+ years of experience collaborating across cross-functional teams (PD, STA, library, CAD, power) with strong written and verbal technical communication skills.

Skills: ML/AI Timing and Power Flow Expert, ASIC/FPGA implementation flows, timing and power convergence, library generation and characterization, ML/AI-driven approaches