Mixed-Signal Verification Engineer – Analog IP - Allen, TX, United States
Originally posted 19 May 2026 by the employer — open 114 days.
This role focuses on verifying analog and mixed-signal IP within the Treo platform.
About the role
This role involves verifying analog and mixed-signal IP integrated into digital-on-top SoC environments. The position focuses on the Treo platform, a high-performance analog and mixed-signal platform built on 65nm Bipolar-CMOS-DMOS (BCD) technology.
What you'll do
- Own mixed-signal verification for assigned analog IP blocks using SystemVerilog and UVM-based methodologies.
- Develop scalable digital-on-top testbenches incorporating behavioral models of analog IP such as PLLs, LDOs, DC/DC converters, and oscillators.
- Translate analog specifications into executable verification plans, assertions, coverage, and checkers.
- Develop and maintain behavioral models using SystemVerilog real-number modeling to abstract analog behavior for system-level simulation.
- Execute regressions, analyze results, and drive debug to root cause across analog, digital, and mixed-signal boundaries.
- Verify configuration, calibration, monitoring, and fault-handling interfaces between analog IP and digital logic.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 6 years of experience in mixed-signal or digital IC verification.
- Strong proficiency in SystemVerilog and UVM-based verification.
- Hands-on experience building behavioral models using Verilog-A/AMS or SystemVerilog real-number modeling.
- Experience verifying analog IP within digital-on-top SoC environments.
Nice to have
- Familiarity with power management or clocking architectures (BGs, PLLs, LDOs, DC/DCs).
- Experience with coverage-driven verification and assertion-based methodologies.
- Exposure to automotive or industrial silicon reliability and safety requirements.
- Interest in automation, scripting, or AI-assisted verification workflows.
Skills: mixed-signal verification, analog IP, SystemVerilog, behavioral modeling, pre-tapeout
This role has been open 113 days — well above the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in category | 2 | 173 |
| Median days open | 145 d | 79 d (+66 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: mixed-signal verification, analog IP, SystemVerilog, behavioral modeling, pre-tapeout
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm · 10 open roles · median 55 d
- Microchip Technology · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.