Mixed Signal IC Layout Engineer - Remote

Originally posted 28 September 2026 by the employer.

About the role

This role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.

What you'll do

• Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
• Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
• Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
• Support post-layout extraction and simulation.

What you'll need

• Experience with full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
• Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout.
• Proficient with Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon.
• Strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.

Nice to have

• Contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.

Skills: full-custom layout, high-speed blocks, Cadence Virtuoso, DRC LVS ERC, FinFET