Mixed Signal Design Verification (MSDV) Engineer - Dallas, United States
Originally posted 8 August 2026 by the employer.
About the role
This role is responsible for pre-tapeout verification of silicon design, ensuring the part will meet all stated specifications and behavior and is manufacturable and testable.
What you'll do
- Drive quality product tapeouts as DV lead.
- Develop pre-Si verification plans, create simulation environments and mixed-signal behavioral models.
- Interface with functional groups to ensure complete product design verification.
- Analyze simulation results, identify root causes of failures, and provide recommendations.
- Participate in design reviews, verification reviews, and silicon bring-up activities.
- Support post-silicon validation and correlation between simulation and measured silicon performance.
What you'll need
- Strong familiarity with EDA design tools such as Cadence Virtuoso design environment.
- Strong familiarity with analog, digital, and mixed-signal design and tool flow.
- Extensive experience with Verilog/Verilog-A/SystemVerilog and Universal Verification Methodology (UVM) to run automated regressions.
- Working knowledge of Unix shell, TCL, Perl, Python, and SKILL scripting languages.
- Bachelor’s, Master’s, or PhD degrees in Electrical Engineering or related field of study.
Nice to have
- Experience developing verification environment for integrated circuits that incorporate I2C, PMBus or SPI type communication protocols.
- Understand power management chip architectures (ideal diodes, e-fuses, switching converters etc).
- Experience with lab validation.
- Understand ESD, reliability, and electro-migration verification.
- Experience with semiconductor manufacturing processes and design-for-test methodologies.
- Familiarity with version control systems such as DesignSync, SVN, Git.
Skills: UVM, SystemVerilog, mixed-signal verification, simulation environments, behavioral models
This role has been open 70 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Nexperia | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1202 |
| Open roles in the wider Digital Design & Verification family | 4 | 3202 · 115 employers |
| Median days open | 70 d | 65 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, mixed-signal verification, simulation environments, behavioral models
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.