Microarchitect and RTL Designer - Compute - Mountain View (HQ) or Remote
$175,000 - $400,000 USD yearly
Originally posted 19 October 2026 by the employer.
About the role
In this role, you own the micro-architecture and RTL end to end for blocks within the compute subsystem, implementing core numerics alongside control and data paths for ML hardware acceleration.
What you'll do
- Contribute to the silicon architecture-to-design methodology across blocks, subsystems, and fullchip design.
- Own entire subsystems, subsets, or chip-level silicon design deliverables from micro-architecture to sign-off-ready design.
- Plan and drive intermediate and sign-off reviews covering micro-architecture, design specifications, execution progress, area, and timing closure toward milestones like design freeze and tapeout.
- Work closely with verification, DFT, and physical design co-owners to deliver performance-power-area targets.
What you'll need
- At least 5 years of silicon design experience with taped-out chips across multiple generations.
- Production-proven experience with silicon micro-architecture and design concepts in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, or memory management.
- Ability and willingness to ramp on Bluespec HDL.
- Experience with SystemVerilog, Python, C/C++, and scripting/programming languages for chip design flows.
- Experience testing designs and collaborating with verification teams toward performance and coverage closure goals.
- Hands-on experience with design synthesis, design lint, and sign-off flows.
Nice to have
- Experience designing arithmetic/compute datapaths for ML, such as matmul / systolic (MAC) arrays, reduction trees, and floating-point / special-function units (e.g. MuFu).
- Prior Bluespec experience or familiarity with functional-programming paradigms (e.g. Haskell).
- Familiarity with verification and emulation platforms and methodologies.
- Experience with logic for moving, storing, or managing data, such as caches, buffers, and crossbars.
This role has been open 2 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | MatX | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 1070 |
| Open roles in the wider Digital Design & Verification family | 30 | 3299 · 116 employers |
| Median days open | 62 d | 62 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.