Memory PHY Architect - CA, Santa Clara, United States
Originally posted 9 October 2026 by the employer.
Shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies.
About the role
This role involves architecting and developing high-speed memory interface IP, specifically shaping digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies.
What you'll do
- Define product features, translate architecture and microarchitecture into technical specifications, and provide technical direction.
- Lead Memory PHY digital architecture development from pathfinding and microarchitecture through RTL implementation, verification, and physical realization.
- Architect and implement PHY link-layer functionality in partnership with analog and system architects.
- Drive analog and digital co-design, digital logic development, RTL coding, and firmware integration for high-speed memory interfaces.
- Guide synthesis, static timing analysis, timing closure, power optimization, and physical implementation.
- Identify complex technical issues and risks, then drive architectural solutions that meet product requirements.
What you'll need
- Collaborative technical leadership with deep curiosity about memory processor architecture, digital design, and high-speed interfaces.
- Clear communication across functions and geographies to build alignment among senior stakeholders.
- Strong analytical judgment with attention to detail.
- Ability to mentor engineers effectively and guide teams through ambiguous design problems.
- A bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Nice to have
- Deep expertise in Memory PHY architecture and implementation, including LPDDR, DDR, GDDR, HBM, SerDes, memory controllers, or other high-speed I/O subsystems.
- Expert proficiency in Verilog or SystemVerilog, digital design methodologies, and scripting languages such as Python, Perl, or Tcl.
- Strong experience with mixed-signal integration, clocking architectures, clock-domain and reset-domain crossing methodologies, low-power design, UPF, synthesis, static timing analysis, timing closure, and silicon bring-up.
- Demonstrated expertise in power-management microarchitecture, low-power design, and power optimization across architecture, logic, and circuit levels.
- Experience guiding technical direction across multiple teams and organizations while building consensus among senior stakeholders.
- Proven ability to mentor engineers, share technical knowledge, and strengthen engineering practices across an organization.
- Strong communication and presentation skills, with the ability to collaborate effectively across disciplines, sites, and time zones.
Skills: Memory PHY, LPDDR, DDR, HBM, SerDes, RTL
This role has been open 0 days — well below the 66-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
303
|
Median days open
66 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (303 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 303 |
| Median days open | 36 d | 66 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: Memory PHY, LPDDR, DDR, HBM, SerDes, RTL
Who's hiring in this category
- Micron Technology · 154 open roles · median 87 d
- Synopsys · 33 open roles · median 50 d
- Qualcomm · 18 open roles · median 93 d
- SanDisk · 17 open roles · median 37 d
- Broadcom · 16 open roles · median 51 d
- NVIDIA · 8 open roles · median 60 d
How we counted: 303 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.