Memory Layout Design Engineer - IND-Bangalore Electronic City - S1, India
Originally posted 3 August 2026 by the employer. Relisted by the employer on 9 September 2026.
About the role
This role is for a Memory Layout Design Engineer responsible for applying layout guidelines, new process rules, and technical requirements to ensure quality layout. The position involves managing scheduling, timelines, and layout floor-planning for end-to-end deliverables within the planned schedule.
What you'll do
- Understand and apply layout guidelines, new process rules, and technical requirements.
- Manage scheduling, timelines, and layout floor-planning.
- Deliver quality layouts from start to finish within the planned schedule.
- Adapt to new methodologies and communicate effectively with SOC/library teams.
What you'll need
- Minimum 3 years of experience with layout knowledge.
- Bachelor's degree.
- Proficiency in Cadence tools (virtuoso layout, layout XL, Cadence schematic capture, CALIBRE, Hercules).
- Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).
- Experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
- Proficiency in floor-planning, hierarchy layout, and chip integration.
- Understanding of memory architecture, RC requirement, and ability to plan signal and power based on layout guidelines.
Nice to have
- Analog layout experience.
- Knowledge of AI, automation in layout, Script Programming, and SKILL Programming.
- Experience with memory compilers.
Skills: Memory layout design, Cadence tools, physical verification, CMOS processes, floor-planning, memory architecture
This role has been open 62 days — below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 287 |
| Median days open | 51 d | 69 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: Memory layout design, Cadence tools, physical verification, CMOS processes, floor-planning, memory architecture
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom (this employer) · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.