Memory Control Design Engineer
$115,600 - $173,400 USD yearly
Originally posted 3 April 2026 by the employer.
About the role
The QCT Memory Controller Design Team is hiring an ASIC Design Engineer responsible for enabling high-speed DDR controllers across QCT products. The focus covers architecture, micro-architecture, logic design, and deployment of memory controllers for LPDDR and PCDDR technologies.
What you'll do
- Develop design specifications and drive the micro-architecture for portions of logic design interfacing to CPU, DSP, and multimedia processors. - Implement and deliver RTL, collaborating closely with verification engineers to deliver high-quality designs. - Debug designs at unit level and provide integration debug support across full-chip environments. - Execute synthesis, timing closure, physical design support, gate-level simulations, and power analysis. - Participate in C/C++ modeling of memory controller IP and contribute to design methodology improvements.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related work experience (or Master's degree with 1+ year, or PhD). - Experience with DDR controller architectures, especially front-end interfaces to CPU, DSP, and multimedia processors. - Experience with x86 or ARM CPU/bus architectures. - Experience in RTL implementation, synthesis, and timing closure.
Skills: DDR Controllers, LPDDR/PCDDR technologies, architecture, RTL, Synthesis, Timing Closure
This role has been open 200 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
310
|
Median days open
69 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (310 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 310 |
| Median days open | 87 d | 69 d (+18 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: DDR Controllers, LPDDR/PCDDR technologies, architecture, RTL, Synthesis, Timing Closure
Who's hiring in this category
- Micron Technology · 158 open roles · median 89 d
- Synopsys · 32 open roles · median 65 d
- Qualcomm (this employer) · 19 open roles · median 86 d
- SanDisk · 17 open roles · median 52 d
- Broadcom · 16 open roles · median 66 d
- NVIDIA · 8 open roles · median 47 d
How we counted: 310 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.