Originally posted 22 October 2026 by the employer.
About the role
As Memory Architect, you will lead the translation of Thermo In-Memory Computing architecture concepts from theory into silicon, reporting to the Director of Silicon Engineering. You will reimagine memory array organization, read/write paths, and microarchitecture that interleaves memory operations with compute primitives.
What you'll do
- Define memory requirements, floorplans, and read/write circuitry to enable Processing-In-Memory capabilities and novel memory primitives.
- Architect local and global datapaths, segmented buses, and on-die fabrics for internal bandwidth and data movement between memory arrays and logic.
- Own power distribution, power budgets, thermal limits, redundancy, and ECC to sustain peak performance, retention, and yield.
- Manage PDK access and design rules, driving tapeout plans from shuttle runs through test-chip bring-up with manufacturing partners.
- Partner with analog engineers to set requirements for primitive device libraries, including write circuits, drivers, and multiplexers.
- Define custom memory host interfaces spanning SERDES, PCIe, Ethernet, DDR5, LP6, or HBM-class interfaces.
- Oversee the development of SPICE, analytical, and cycle-level models for performance, power, and yield validation.
What you'll need
- Substantial experience in memory architecture or circuit design at a memory manufacturer or memory-centric compute company.
- Deep understanding of memory array physics across 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability.
- Hands-on experience with embedded memory or random access memory technology, PDKs, and developing memory test chips through tapeout.
- Proficiency moving between SPICE-level circuit behavior and architecture-level performance and power models using Python, C, or C++.
- Experience in RTL and SystemVerilog to model and optimize dataflow and specify compute block requirements.
- Experience with different interface types including memory interfaces.
Nice to have
- Experience with process-in-memory or near-memory compute.
- Experience with non-volatile memory technology.
- Experience with DRAM technology including eDRAM.
- Major publications at ISSCC, VLSI, IEDM, ISCA, or other major conferences.
- Existing relationships with manufacturers.
Skills: memory architecture, in-memory compute, DRAM bitcells, SRAM, read/write paths, PDK
This role has been open 14 days — well below the 72-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
302
|
Median days open
72 d
|
Category median salary (all employers)
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Normal Computing | All employers we track in this specialty (302 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 302 |
| Median days open | 17 d | 72 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: memory architecture, in-memory compute, DRAM bitcells, SRAM, read/write paths, PDK
Who's hiring in this category
- Micron Technology · 154 open roles · median 82 d
- Synopsys · 30 open roles · median 77 d
- Qualcomm · 18 open roles · median 106 d
- Broadcom · 16 open roles · median 78 d
- SanDisk · 15 open roles · median 7 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 302 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.
