Member of Technical Staff, SoC Power and Physical Architect, Next-generation HBM Architecture
$191,000 - $334,000 USD yearly
Originally posted 10 July 2026 by the employer.
About the role
This role involves driving SoC-level specification for 3D-stacked, high-performance memories.
What you'll do
- Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces.
- Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation.
- Define DFT architectures (e.g., scan chain topology) and set verification requirements.
- Define SoC floorplans in collaboration with physical designers.
- Compose and maintain clear SoC physical documentation.
What you'll need
- Experience with high-bandwidth memory (HBM) architectures.
- Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
- 8+ years of industry experience delivering SoC hardware designs.
Nice to have
- Experience with circuit design, including IP interface requirements, power delivery behavior, and clocking constraints.
- Familiarity with chip-level thermal analysis and power hotspot mitigation strategies.
- Experience reasoning about interconnects and frequency vs. energy/power tradeoffs.
- Experience with synthesis, static timing analysis, and relevant EDA toolsets: PrimePower, PrimeShield, RedHawk, and ICC2.
Skills: SoC microarchitecture, clocking architectures, power delivery networks, thermal analysis, DFT architectures
This role has been open 190 days — well above the 75-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
442
|
Median days open
75 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (442 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 442 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 121 d | 75 d (+46 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: SoC microarchitecture, clocking architectures, power delivery networks, thermal analysis, DFT architectures
Who's hiring in this category
- Qualcomm · 71 open roles · median 82 d
- NVIDIA · 57 open roles · median 59 d
- AMD · 36 open roles · median 61 d
- Arm Holdings · 27 open roles · median 102 d
- Renesas Electronics · 22 open roles · median 59 d
- NXP Semiconductors · 20 open roles · median 104 d
How we counted: 442 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.