Member of Technical Staff - Physical Design - Palo Alto, United States
Originally posted 14 September 2026 by the employer.
About the role
As the first Physical Design engineer, you will build the physical design function and extend the AI system from spec-to-netlist to tapeout-ready GDS. You will own methodology and hands-on execution for physical implementation at 3nm, 2nm, and future nodes.
What you'll do
- Build and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
- Drive block and full-chip floorplanning, power planning, placement, clock tree synthesis, routing, and ECOs.
- Define release criteria and close timing, signal integrity, EM/IR, DRC/LVS, and foundry-required physical checks through final GDS delivery.
- Translate Physical Design expertise into automated flows, structured tool feedback, and evaluations.
- Resolve process, library, tool, and signoff challenges directly with foundries, EDA vendors, and IP providers.
- Set technical standards, define the Physical Design roadmap and hiring priorities, and mentor future hires.
What you'll need
- Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure.
- A track record of building production Physical Design methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs.
- Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity.
- Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, along with commercial timing, extraction, power integrity, and physical verification tools.
- Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting.
- Ability to independently establish the flow, debug difficult closure problems, and explain implementation trade-offs to hardware, software, and AI teams.
Nice to have
- Direct 2nm methodology bring-up and tapeout experience, including GAA/nanosheet implementation and evolving PDK or library qualification.
- Implementation of high-performance CPUs, GPUs, AI accelerators, or complex custom SoCs with demanding frequency and power targets.
- Experience with design-technology co-optimization, chiplets, multi-die integration, or backside power delivery where supported by the target process.
- Prior experience as a founding Physical Design engineer or building methodology adopted across multiple teams and chip programs.
Skills: netlist-to-GDS, tapeout, floorplanning, placement, signoff
This role has been open 37 days — well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 664 |
| Open roles in the wider Physical Implementation family | 1 | 1484 · 110 employers |
| Median days open | 37 d | 62 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: netlist-to-GDS, tapeout, floorplanning, placement, signoff
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 61 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 67 d
- Synopsys · 38 open roles · median 36 d
- Broadcom · 35 open roles · median 101 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.