Member of Technical Staff - ML Research - Palo Alto, United States
Originally posted 10 February 2026 by the employer.
Train AI models and reinforcement learning workflows for chip design targeting TSMC foundry technologies.
About the role
As a Member of the Technical Staff at Architect Labs, you will train AI models for chip design, verification, and exploration tasks. This work applies fundamental research to production chips targeting foundry processes like TSMC.
What you'll do
- Co-design and implement reinforcement learning environments and algorithms, reward model training, and reward signal experiments. - Implement, scale, and improve post-training techniques to enhance model capabilities and usability for chip designs. - Design, build, and run pipelines for model fine-tuning and evaluation to deliver production-ready implementations. - Own the end-to-end RL workflow, spanning reward modeling, environment design, test-time optimization, and scaling. - Collaborate with research teams to translate emerging techniques into production implementations while debugging training pipelines and model behaviors.
What you'll need
- PhD in Computer Science, Computer Engineering, EECS, Mathematics, or a related field (or BS/MS with equivalent research engineering experience). - Deep expertise in reinforcement learning and post-training, with experience deploying models from research to production. - Experience building end-to-end ML pipelines, including RL and fine-tuning LLMs and code models for reasoning, tool use, and structured coding. - Software engineering experience with large-scale distributed systems, high-performance computing, and distributed training frameworks such as PyTorch, CUDA, QLoRA, and ZeRO. - Demonstrated ability to analyze, benchmark, and debug model training processes with operational reliability.
Nice to have
- Prior work on post-training teams at frontier research labs such as OpenAI, Anthropic, DeepMind, Mistral, MSL, or Cohere. - Background in electrical engineering, computer engineering, computer architecture, chip design, or verification processes. - Publications in ML conferences (NeurIPS, ICLR, ICML) or EDA conferences (DAC, ICCAD, DVCon). - Experience as a founding ML engineer/researcher or early hire at an AI startup.
Skills: reinforcement learning, ai models, chip design, fine-tuning llms, ml pipelines
This role has been open 130 days — well above the 89-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
507
|
Median days open
89 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (507 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 507 |
| Open roles in the wider Software, Firmware & Systems family | 4 | 6292 · 146 employers |
| Median days open | 130 d | 89 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: reinforcement learning, ai models, chip design, fine-tuning llms, ml pipelines
Who's hiring in this category
- Qualcomm · 104 open roles · median 118 d
- NVIDIA · 88 open roles · median 60 d
- AMD · 32 open roles · median 110 d
- Micron Technology · 27 open roles · median 62 d
- Mobileye · 20 open roles · median 88 d
- Analog Devices · 18 open roles · median 45 d
How we counted: 507 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.