Member of Technical Staff - Microarchitectural Validation - Palo Alto, United States
Originally posted 16 April 2026 by the employer.
About the role
As a Member of Technical Staff on the Design Verification & Validation team, you will own the verification strategy for designs taping out on foundries. You will work on hardware verification and AI-driven design automation across internal and external SoC projects.
What you'll do
- Review test plans and validation strategy for internal and external SoC projects. - Provide domain-specific expertise to AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols. - Define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs. - Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral. - Track emerging trends in semiconductor verification and design automation methodology.
What you'll need
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. - 5+ years of experience working on advanced-node tapeouts at chip companies or silicon startups. - Experience with SystemVerilog, UVM, and C/C++ for test environments. - Hands-on verification experience in at least one area: ARM/AMBA protocols (APB, AHB, AXI, ACE), CPU subsystems, memory controllers and PHY (LPDDR/DDR), on-chip interconnect/NoC, NPU/ML accelerator cores, or security IPs. - Hands-on experience with simulation and emulation methodologies, or mapping IP and SoC designs to FPGA prototypes for functional verification. - Experience defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing reusable validation collateral.
Nice to have
- SoC-level DV experience bringing up full systems with memory controller, PHY, and CPU connectivity, validating top-level integration. - Experience with AMBA protocols, specifically ACE for coherent CPU-memory access. - FPGA prototyping experience with Xilinx Vivado/Vitis. - Verification experience spanning multiple areas: interconnects, CPU subsystems, ARM AMBA, memory controllers, and NPUs. - Python programming skills.
Skills: tapeout experience, UVM, SystemVerilog, emulation, functional verification
This role has been open 130 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1268 |
| Open roles in the wider Digital Design & Verification family | 6 | 3359 · 116 employers |
| Median days open | 114 d | 67 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: tapeout experience, UVM, SystemVerilog, emulation, functional verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.