Member of Technical Staff - Formal Verification - Palo Alto, United States
Originally posted 17 August 2026 by the employer.
About the role
As a Member of Technical Staff, Formal Verification at Architect Labs, you will own formal verification of AI-generated chip design artifacts from early specifications through tape-out. You will turn design intent into assertions, build formal environments, and formally verify complex designs.
What you'll do
- Develop and execute formal verification plans using AI for hardware blocks and subsystems.
- Drive proofs to completion using abstraction, decomposition, invariants, and appropriate solver strategies.
- Debug counterexamples, isolate root causes, and work with RTL designers to resolve issues.
- Assess verification completeness through coverage analysis, reachability checks, vacuity checks, and assumption reviews.
- Build reusable verification components and automate formal regressions, result tracking, and failure triage.
What you'll need
- Degree: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- RTL and Assertions: Strong SystemVerilog and SVA skills.
- Formal Tools: Hands-on experience with tools such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal.
- Proof Techniques: Practical understanding of model checking, induction, abstraction, and assume-guarantee reasoning.
- Hardware Understanding: Comfortable reasoning about control logic, pipelines, arbitration, buffering, and interface protocols, including reset behavior, backpressure, and concurrent transactions.
- Engineering Rigor: Strong scripting skills in Python, Tcl, or similar languages.
Nice to have
- Experience owning formal verification sign-off for blocks or subsystems in a shipped chip.
- Experience verifying AI accelerators, processor cores, cache coherence, memory systems, or interconnects.
- Background in simulation-based verification and UVM.
- Experience building formal verification infrastructure used across multiple projects or teams.
- Familiarity with AI-generated RTL or using verification results to guide automated design and repair.
- Experience as an early technical hire at a semiconductor or EDA startup.
Skills: Formal Verification, formal methods, SMT solvers, model checkers, proof assistants, formal specification language
This role has been open 71 days — slightly above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1268 |
| Open roles in the wider Digital Design & Verification family | 6 | 3359 · 116 employers |
| Median days open | 114 d | 67 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Formal Verification, formal methods, SMT solvers, model checkers, proof assistants, formal specification language
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.