Member of Technical Staff - Formal Methods - Palo Alto, United States
Originally posted 13 May 2026 by the employer.
About the role
As a Member of Technical Staff - Formal Methods at Architect Labs, you will work on the formal foundations of the chip design flow, taking AI-generated hardware artifacts into verified production-grade silicon. You will own the formal stack end-to-end, including specification language, intermediate representation, proof obligations, and solver integration.
What you'll do
- Design and implement the formal specification language and intermediate representation across hardware specifications, testbenches, assertions, and RTL. - Build the proof-obligation generator to emit checkable claims and develop the toolchain discharging them via SMT solvers, model checkers, and proof assistants. - Establish soundness arguments and coverage-adequacy methodology to demonstrate that generated artifacts faithfully characterize the specification. - Co-design with verification methodology and ML research teams to establish boundaries between provable and tested domains.
What you'll need
- PhD in Computer Science, EECS, or a closely related field with research in formal methods applied to hardware or systems, or a BS/MS with a strong industrial track record in formal verification. - Deep expertise in at least two of: temporal logic and model checking, SMT-based verification, refinement-based specification, or proof assistants applied to hardware, distributed, concurrent, or low-level systems. - Experience with formal frameworks or proof tools such as TLA+, Lean, Coq, or similar. - Demonstrated history of applying formal methods to real, shipped artifacts rather than only published proofs. - Software engineering capability to build compiler-style infrastructure and integrate formal tools into automated pipelines.
Nice to have
- Industrial formal verification experience at silicon companies, automated reasoning groups, or specialized formal methods firms. - Experience with design of HLS (High-Level Synthesis) tools. - Background in compiler/IR design or DSL implementation used by engineers. - Publications at formal methods, PL, or EDA venues such as CAV, FMCAD, POPL, PLDI, TACAS, DAC, ICCAD, or DVCon. - Familiarity with modern AI/ML systems and how learned components interact with formal guarantees. - Experience as an early technical hire at a deeptech or formal-methods startup.
Skills: formal methods, chip design flow, SMT solvers, model checkers, proof assistants
This role has been open 130 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1268 |
| Open roles in the wider Digital Design & Verification family | 6 | 3359 · 116 employers |
| Median days open | 114 d | 67 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal methods, chip design flow, SMT solvers, model checkers, proof assistants
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.