Member of Technical Staff - AI for Chip Design - Palo Alto, United States
Originally posted 23 April 2026 by the employer.
About the role
As a Member of the Technical Staff - AI for Chip Design, you will translate hardware engineering expertise into agentic systems that reason about, generate, and verify silicon. You will focus on building AI agents that tackle core chip-design tasks and compress end-to-end software to silicon timelines.
What you'll do
- Design and build AI agents that tackle core chip-design tasks, grounding model behavior in hardware engineering workflows. - Own end-to-end agent workflows including scaffolding, tool use, evaluation harnesses, and domain-specific infrastructure. - Curate high-quality data, define evaluation criteria, and encode engineering judgment to evaluate outputs. - Partner with ML research, post-training, and infrastructure teams to convert hardware domain expertise into reward signals, benchmarks, and training signals. - Prototype, evaluate, iterate, and translate ambiguous chip-design challenges into deployed agent capabilities.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, EECS, or a closely related field. - Industry or research experience as an RTL design or Design Verification engineer, with an understanding of the end-to-end modern chip design flow. - Software engineering fundamentals with the ability to write production-grade Python or TypeScript and build tooling in modern engineering environments. - Demonstrated ability to prototype quickly and productionize solutions for ambiguous engineering problems. - Interest in applying frontier AI to hardware design workflows.
Nice to have
- Prior experience on AI-for-chip-design or AI4EDA efforts at Google, NVIDIA, or chip / EDA companies. - Experience building, using, or evaluating LLM-based tooling for engineering workflows. - Publications or open-source contributions at the intersection of ML and EDA (DAC, ICCAD, DVCon, MLCAD, NeurIPS, ICLR, ICML). - Experience as an early engineer at a deeptech or AI startup.
Skills: AI agents, chip-design tasks, hardware engineering, silicon, RTL design, Design Verification
This role has been open 130 days — well above the 89-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
507
|
Median days open
89 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Architect Labs | All employers we track in this specialty (507 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 507 |
| Open roles in the wider Software, Firmware & Systems family | 4 | 6292 · 146 employers |
| Median days open | 130 d | 89 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: AI agents, chip-design tasks, hardware engineering, silicon, RTL design, Design Verification
Who's hiring in this category
- Qualcomm · 104 open roles · median 118 d
- NVIDIA · 88 open roles · median 60 d
- AMD · 32 open roles · median 110 d
- Micron Technology · 27 open roles · median 62 d
- Mobileye · 20 open roles · median 88 d
- Analog Devices · 18 open roles · median 45 d
How we counted: 507 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.