Manager, DRAM Final Test Applications Engineering (Memory Test; San Jose, CA)
$189,800 - $303,700 USD yearly
Originally posted 2 October 2026 by the employer.
About the role
This role involves leading a team of Applications Engineers to support memory semiconductor manufacturers worldwide in the successful deployment of advanced DRAM production test solutions.
What you'll do
- Lead, mentor, and develop a team of Applications Engineers supporting global DRAM customers.
- Establish team priorities, resource plans, and organizational capabilities.
- Lead strategic customer engagements, technical escalations, device bring-up activities, and production ramps.
- Provide technical leadership for advanced DRAM production test solutions, focusing on test methodology development, characterization, and yield improvement.
- Partner with Engineering, Product Management, Marketing, and Sales teams to influence hardware and software roadmaps.
- Represent customer requirements and industry trends to support product strategy and business growth.
What you'll need
- BSEE, MSEE, or related technical degree, or equivalent industry experience.
- 15+ years of semiconductor test experience with a strong focus on memory products.
- 5+ years of engineering leadership experience managing technical teams, projects, or customer-facing engineering organizations.
- Demonstrated success supporting customer product introductions, production ramps, and high-volume manufacturing deployments.
- Proven experience leading complex technical escalations and strategic customer engagements.
- Deep expertise in DRAM final test methodologies, high-volume manufacturing, and production test deployments supporting DDR, LPDDR, and GDDR memory technologies.
- Strong understanding of high-speed memory interfaces, signal integrity, timing analysis, jitter characterization, eye diagram evaluation, and tester-to-system correlation.
- Strong knowledge of device characterization, yield improvement, test coverage optimization, and production test methodologies.
- Strong hardware and software debug capabilities with experience developing and deploying automated production test solutions.
- Proficiency with C/C++ or comparable software development environments.
Nice to have
- Experience with HBM, NAND Flash, and memory wafer sort test environments.
- Experience with Nextest Magnum, Advantest, or similar memory test platforms.
- Experience supporting AI, graphics, mobile, or high-performance computing memory products.
- Familiarity with advanced memory packaging technologies.
- Experience managing globally distributed engineering teams.
This role has been open 7 days — well below the 24-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
523
|
Median days open
24 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (523 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 68 | 523 |
| Open roles in the wider Silicon Validation & Test family | 85 | 2209 · 111 employers |
| Median days open | 22 d | 24 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne (this employer) · 67 open roles · median 21 d
- Infineon Technologies · 39 open roles · median 35 d
- Renesas Electronics · 39 open roles · median 24 d
- AMD · 28 open roles · median 36 d
- Micron Technology · 28 open roles · median 30 d
- Qualcomm · 25 open roles · median 23 d
How we counted: 523 open Silicon Test Engineering (DFT Test) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.