Manager/Director of Hardware Engineering - Santa Clara, California, United States
Originally posted 2 July 2026 by the employer.
About the role
As Manager/Director of Hardware Engineering, you will lead a team of RTL microarchitects and design verification engineers owning the end-to-end execution of high-speed interconnect IP blocks. The focus centers on software-driven, unified fabric solutions for single-die and multi-die systems.
What you'll do
- Directly manage, mentor, and grow a team of 8-12 RTL and DV engineers.
- Drive the development of high-speed interconnect IP from microarchitecture specifications to RTL implementation and tape-out.
- Oversee the development of robust, coverage-driven verification test plans, UVM/OVM environments, and emulation platforms.
- Work closely with architecture, physical design, and system teams to balance power, performance, area (PPA), and timing requirements.
- Define and establish engineering metrics, standard methodologies, and agile project management tools to meet tape-out milestones.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of industry experience in ASIC/IP development, with at least 2-3 years in a technical leadership or management role.
- Strong background in high-speed protocols (such as PCIe, UCIe, CXL, Ethernet, or advanced SerDes).
- Proficiency in SystemVerilog, Verilog, and industry-standard EDA simulation/synthesis flows.
- Deep understanding of modern verification methodologies (UVM/OVM), constrained random testing, formal verification, and coverage analysis.
Skills: RTL, SystemVerilog, UCIe, UVM, high-speed interconnect, multi-chiplet
This role has been open 88 days — well above the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1036
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Baya Systems | All employers we track in this specialty (1036 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1036 |
| Open roles in the wider Digital Design & Verification family | 11 | 3224 · 116 employers |
| Median days open | 88 d | 61 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL, SystemVerilog, UCIe, UVM, high-speed interconnect, multi-chiplet
Who's hiring in this category
- Qualcomm · 140 open roles · median 65 d
- Synopsys · 86 open roles · median 33 d
- AMD · 71 open roles · median 39 d
- Analog Devices · 47 open roles · median 51 d
- NVIDIA · 42 open roles · median 61 d
- NXP Semiconductors · 42 open roles · median 87 d
How we counted: 1036 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.