Manager Design Verification - Tel Aviv-Yafo, Tel Aviv District, Israel
Originally posted 14 September 2026 by the employer — open 0 days.
About the role
This role involves owning design execution on complex blocks across purpose-built connectivity products. You will work on PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.
What you'll do
- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
- Develop high-quality, synthesizable Verilog/SystemVerilog.
- Drive design reviews, lint, CDC, and timing closure activities.
- Partner with architecture to translate specifications into implementation-ready microarchitecture.
- Collaborate with verification on testplans, coverage closure, and bug triage.
- Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of digital design experience, including at least one full chip from spec to tapeout.
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
- Familiarity with formal verification, emulation, or assertion-based methodologies.
- Background in advanced process nodes (7nm, 5nm, or below).
- Strong debug skills across pre-silicon and post-silicon environments.
Skills: RTL design, Verilog/SystemVerilog, synthesis, PCIe, CXL, Ethernet
This role has been open 0 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
933
|
Median days open
66 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (933 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 933 |
| Open roles in the wider Digital Design & Verification family | 43 | 3056 · 116 employers |
| Median days open | 60 d | 66 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: RTL design, Verilog/SystemVerilog, synthesis, PCIe, CXL, Ethernet
Who's hiring in this category
- Qualcomm · 135 open roles · median 55 d
- AMD · 59 open roles · median 66 d
- NXP Semiconductors · 52 open roles · median 63 d
- NVIDIA · 48 open roles · median 48 d
- Synopsys · 44 open roles · median 64 d
- Marvell Technology · 41 open roles · median 119 d
How we counted: 933 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.