LPDDR PHY IP Verification Engineer
Originally posted 21 September 2026 by the employer.
Join the LPDDR PHY IP team.
About the role
This role involves developing test benches and verifying integrated IP Subsystems. You will be contributing to the LPDDR PHY IP team.
What you'll do
- Develop test benches
- Verify integrated IP Subsystems
What you'll need
- BSEE with 6+ years of relevant experience or MSEE with 3+ years of relevant experience
- Experience in ASIC RTL design and verification at the chip level and block level
- Strong Verilog, System Verilog, UVM, PERL, and TCL skills
- Knowledge in silicon debugging
Nice to have
- Knowledge of high speed interface protocols
Skills: LPDDR, PHY, UVM, SystemVerilog, test benches
This role has been open 0 days — well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1172
|
Median days open
59 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1172 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 1172 |
| Open roles in the wider Digital Design & Verification family | 137 | 3097 · 114 employers |
| Median days open | 19 d | 59 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: LPDDR, PHY, UVM, SystemVerilog, test benches
Who's hiring in this category
- Qualcomm · 113 open roles · median 48 d
- AMD · 106 open roles · median 34 d
- NVIDIA · 88 open roles · median 70 d
- Synopsys (this employer) · 63 open roles · median 19 d
- SiFive · 54 open roles · median 51 d
- Micron Technology · 53 open roles · median 106 d
How we counted: 1172 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.