Low-Power Feature Validation & Bring-Up Engineer - CA, Santa Clara, United States
Originally posted 28 July 2026 by the employer.
About the role
NVIDIA's Silicon Co-Design Group is seeking an engineer to develop low-power silicon validation and system bring-up methodologies across pre-silicon and post-silicon environments. The role focuses on scaling low-power validation through telemetry pipelines, intelligent automation, and debug workflows across product generations.
What you'll do
- Define Power & Performance validation strategies across product lines, including power targets, rail budgets, and low-power feature validation methodologies. - Build workload characterization frameworks using telemetry, behavioral clustering, and analytics to identify power-state and data-path issues. - Define instrumentation, counters, telemetry frameworks, and firmware hooks to enable silicon observability and automated validation before tapeout. - Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using automation and debug techniques. - Develop infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation. - Partner with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to construct scalable validation pipelines and dashboards.
What you'll need
- BS or MS in EE, CE, CS, Systems Engineering, or equivalent experience. - 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization. - Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies. - Experience building scalable automation, telemetry analytics, or automated engineering workflows for silicon validation, debug, or productization. - Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills. - Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
This role has been open 156 days — well above the 72-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
114
|
Median days open
72 d
|
Median salary
$185k
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See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (114 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 114 |
| Open roles in the wider Silicon Validation & Test family | 85 | 2238 · 112 employers |
| Median days open | 78 d | 72 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 45 d
- AMD · 16 open roles · median 72 d
- NVIDIA (this employer) · 12 open roles · median 75 d
- Graphcore · 10 open roles · median 129 d
- Altera · 5 open roles · median 65 d
- Micron Technology · 5 open roles · median 219 d
How we counted: 114 open Post-Silicon Validation (Design Verification) roles from 31 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.